Actborne

siliconmind

Antes del lanzamiento, Harden the flow (pre-silicon)

Datos de la empresa

Archivo registrado
company/siliconmind/company.yaml
Propósito
siliconmind, an AI-native chip-design house.
Etapa declarada
Antes del lanzamiento. Declarada por el archivo de la empresa; aún sin evidencia pública.
Capacidad demostrada
Ninguna publicada.
Siguiente paso útil
Aún no hay nada público que probar. Para preguntar por esta empresa, escribe a hello@actborne.com
Sitio comercial
El archivo de la empresa no indica ninguno.
Fase actual
Harden the flow (pre-silicon)
Objetivo de esta fase
Deploy the API to staging; fix the partially-broken core flow; run an end-to-end DRY-RUN (spec → RTL → synth → P&R → signoff → clean GDS on Sky130) with the DRC/LVS gate BLOCKING a deliberately-dirty GDS, and ZERO unsigned-off tapeout attempts. No real money, no shuttle.

Idioma de origen: en. El texto propio de la empresa en esta página se mantiene en inglés, el idioma de su archivo.

Principios

  1. Artículo 1

    A design is a falsifiable claim. Every Design ships with a predicted PPA (power/performance/area) and a calibrated confidence.

  2. Artículo 2

    Silicon is the only proof. Success is a fabricated chip passing bring-up, never a clean signoff report or a passing simulation.

  3. Artículo 3

    The signoff is ours and non-negotiable. Every GDS is DRC+LVS-clean by siliconmind's own signoff before it leaves for a foundry.

  4. Artículo 4

    A non-clean GDS never tapes out. A shuttle slot is real money and months of latency; the DRC/LVS gate is the comparator.

Límites permanentes

  • We will not submit a GDS to any foundry or shuttle without a passing, siliconmind-run DRC+LVS signoff (100% clean)

    Clean-before-tapeout is the hard gate that defines siliconmind; bound by metrics.drc_lvs_clean_gds_rate (== 1.0) + unsigned_off_tapeout_attempts (== 0).

  • We will not design, optimize, broker, or tape out export-controlled or weapons-system silicon (EAR/ITAR/Wassenaar dual-use)

    No campaign, customer, or price clears a controlled design. There is no approval path.

  • We will not incorporate third-party IP we are not licensed for, nor reverse-engineer a competitor's netlist or GDS

    IP integrity is the trust contract with every customer. A flow that launders unlicensed IP is uninsurable and unsellable.

Extracto del archivo

company/siliconmind/company.yaml extracto
  1. metadata:
  2. name: siliconmind
  4. identity:
  5. principles:
  6. - A design is a falsifiable claim. Every
  7. Design ships with a predicted PPA
  8. (power/performance/area) and a
  9. calibrated confidence.
  10. - Silicon is the only proof. Success is a
  11. fabricated chip passing bring-up, never
  12. a clean signoff report or a passing
  13. simulation.
  15. lifecycle:
  16. current_phase: phase_0_harden_flow # Harden the flow (pre-silicon)